Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template
نویسنده
چکیده
Many contemporary servers, personal and laptop computers, and even cell phones are powered by highperformance superscalar processors.A growing body of work has compiled a strong case for employing microarchitecturally diverse superscalar cores in both general-purpose and embedded systems. • Future general-purpose microprocessors will consist of many cores. This makes it possible to provide multiple, differently-designed superscalar core types for streamlining the execution of sequential [10][13][18][19], parallel [6][17][20][27], and multiprogrammed [11][12] workloads, by exploiting diversity across and within applications.
منابع مشابه
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques to rapidly explore and evaluate candidate architectures based on area, power, and performance constraints. We present an exploration framework for pipelined process...
متن کاملImpact of the Interconnect on Performance and Area/Power for High Core Count (> 8) CMPs
Introduction Faithful to Moore’s law, silicon processing improvements have continually increased the number of transistors available for implementing CPUs within a fixed die area. The designer is left with the choice of how to put those transistors to use. Superscalar processors are organized into parallel pipelines which aggressively seek to execute instructions within a single thread in paral...
متن کاملNehalem Processor Core Made FPGA Synthesizable
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-oforder micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlik...
متن کاملStream and Memory Hierarchy Design for Multi-Purpose Accelerators
Power and programming challenges make heterogeneous multi-cores composed of cores and ASICs an attractive alternative to homogeneous multi-cores. Recently, multi-purpose loop-based generated accelerators have emerged as an especially attractive accelerator option. They have several assets: short design time (automatic generation), flexibility (multi-purpose) but low configuration and routing ov...
متن کاملCo-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper proposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely used communication protocol for emulation, and an FPGA-based emulation platform. A high-level (S...
متن کامل